Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
In some programmable ICs, configuration memory cells are organized by frames for addressing configuration memory cells for purposes of programming and reading back the states of the configuration memory cells. A frame is the smallest quantity of configuration memory cells that can be programmed, and the configuration memory cells of a frame control many tiles of an FPGA. That is, in order to program certain configuration memory cells of a frame, all the configuration memory cells in the frame need to be programmed, which affects all the tiles covered by the frame.
A partially configurable portion of a circuit design refers to one or more modules for which a configuration bitstream can be generated and used to partially configure the FPGA. The remaining modules of the design are not required for the partially configurable portion of the design to be initially implemented on the FPGA. A partially reconfigurable portion of the design refers to one or more modules that have different implementations in separate configuration bitstreams. For a partially reconfigurable portion of the design, the FPGA is configured with a first bitstream to implement a first version of the PR modules. Subsequently, the FPGA is partially reconfigured to implement a second version of the PR modules. A static portion of the circuit design refers to one or more modules that are not subject to partial reconfiguration once implemented on the FPGA. A partially configurable module may be static if it is not subject to partial reconfiguration. The term “partial programming” may be used to refer to partial configuration and partial reconfiguration.
For designs having a module that is subject to partial reconfiguration and/or partial configuration, the implementation of the module must occupy entire frames. A frame of configuration memory cells cannot be programmed to implement both a static part of the design and the partially reconfigurable and/or partially configurable module without causing dynamic logic (e.g., block RAM or lookup table RAM) of the static part of the frame to glitch during reconfiguration.